1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to techniques for enhancing performance characteristics of a compilable read-only memory (ROM) instance.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a xe2x80x9cdesign gapxe2x80x9d between today""s electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers"" productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the xe2x80x9cdeep submicronxe2x80x9d problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, nonvolatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other xe2x80x9cnon-logicxe2x80x9d cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design reuse is through what are known as Intellectual Property (xe2x80x9cIPxe2x80x9d) componentsxe2x80x94pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory, including ROM, is a key technology driver for SOC design. It is also well known that speed and power consumption are two major factors in designing a high performance ROM core. In typical ROM architectures, a transistor is placed at the intersection of every bitline (BL) and wordline (WL) with the transistor"" gate being connected to the WL. Depending on the actual ROM code to be programmed, the transistor of the bit cell is either connected to the BL (for storing a binary 0) or left open (for storing a binary 1).
It should be appreciated that as the number of binary 0""s on a BL increases, its capacitance also increases because of the parasitic diffusion capacitance of the transistor""s drain connected thereto. It is possible that in some instances the ROM code to be programmed may have a large number of 0""s on one or more BLs, resulting in degraded performance with respect to both speed and power. First, as more 0""s are programmed on a BL, that particular BL will discharge more often during access cycles because of its pre-charge condition. This, in turn, implies that the BL will consume more power for bringing it back to a pre-charge condition relative to a BL that has more 1""s. Further, the same power consumption constraints also apply to the entire ROM core on a per input/output (I/O) block basis even where individual BL loading of binary 0""s is relatively comparable across the BLs of a particular I/O block.
In addition, having more 0""s on a BL results in larger parasitic capacitance which leads to a slower rate of discharge. Consequently, access time characteristics of the ROM are severely degraded. Clearly, this leads to undesirable operating conditions for high performance embedded applications.
Based on the foregoing, it should be readily recognized that there has arisen an acute need for an effective yet efficient solution that increases performance characteristics of ROMs without incurring unacceptable penalties in silicon area, design complexity, or process flow required for its implementation. It would be of further advantage that the solution be adaptable for compilable ROM architectures so that increased performance may be realized in embedded applications as well.
Accordingly, the present invention is directed to providing techniques for increasing performance by reducing bitline capacitance (hence increasing speed and lowering power consumption) in a compilable ROM core by manipulating the distribution of the binary contents therein.
In one aspect, the present invention is directed to a technique wherein row and column addresses are scrambled for achieving a desired distribution of the data map to be programmed into the ROM. Upon providing a predetermined data map, the number and distribution of binary 0""s and 1""s in the ROM are analyzed under normal row and column addressing. Thereafter, a select portion of the row addresses is interchanged with a select portion of the column addresses and the distribution of 0""s and 1""s is analyzed again under the scrambled addressing scheme. This process of scrambling addresses and comparing the resultant distributions of the binary data may take place until various possible combinations of row and column address interchanging have been verified. Subsequently, a particular addressing scheme is selected for programming the ROM with the pattern having the best possible distribution of 0""s and 1""s that optimizes speed and power.
In another aspect, the present invention is directed to a compilable ROM having a data map programmed with a scrambled addressing scheme wherein at least a portion of the row and column addresses is interchanged therebetween. The interchanged addressing scheme is determined upon analyzing the distribution of 0""s and 1""s of the ROM code under various combinations of scrambling between the row and columns addresses. By minimizing the bitline loading of 0""s in the ROM core, speed is gained and power consumption is reduced.
A more complete understanding of the present invention may be had by reference to the following Detailed Description when taken in conjunction with the accompanying drawings wherein:
FIG. 1 depicts an architectural view of a presently preferred exemplary embodiment of a read-only memory (ROM) portion wherein the teachings of the present invention may be advantageously practiced;
FIG. 2 is a flow chart of the steps involved in an exemplary technique for increasing performance in a ROM in accordance with teachings of the present invention, wherein the contents of an I/O block are inverted in order to minimize the loading of 0""s therein;
FIGS. 3A and 3B depict an exemplary data map for a ROM with two I/O blocks for illustrating the technique of data inversion per I/O;
FIG. 4A depicts exemplary output path circuitry that includes a selectively activatable inverted path portion for facilitating accurate reading of the original data in a ROM having an I/O with inverted data;
FIG. 4B depicts an exemplary layout of two metal mask layers for providing vias therebetween that are selectively fabricated during a mask-level programming step of the ROM fabrication process;
FIG. 5 is a flow chart of the steps involved in another exemplary technique for increasing performance in a ROM in accordance with teachings of the present invention, wherein the contents of a select bitline in an I/O block are inverted in order to minimize its capacitive loading;
FIGS. 6A and 6B depict an exemplary data map for a ROM with two I/O blocks for illustrating the technique of data inversion per bitline;
FIG. 7A depicts exemplary output path circuitry that includes a selectively activatable inverted path portion for facilitating accurate reading of the original data in a ROM having bitlines with inverted data;
FIGS. 7B and 7C depict exemplary logic circuitry for generating control signals for selectively enabling an inverted output path portion for the ROM having bitlines with inverted data;
FIG. 8 is a flow chart of the steps involved in a generalized methodology for increasing performance in the ROM in accordance with the teachings of the present invention, wherein the contents of a select ROM portion are manipulated in order to achieve a predetermined binary data distribution condition;
FIGS. 9A and 9B depict a flow chart of the steps illustrating yet another technique for increasing performance in the ROM in accordance with teachings of the present invention, wherein row and column addresses of the ROM are scrambled to re-distribute the binary data; and
FIGS. 10A and 10B depict a single I/O ROM example for illustrating the technique of address scrambling in order to achieve a predetermined binary data distribution condition that optimizes speed and power consumption of the ROM.